Embodiments of the present invention relate to a static random access memory (SRAM), particularly an SRAM with buffered-read bit cells and its testing.
Shrinking semiconductor integrated circuit feature sizes have placed increasing challenges on semiconductor integrated circuit processing. In particular, a balance between high packing density and yield requires a finely tuned manufacturing process. Minimum feature sizes of high density memory cells are frequently less than corresponding feature sizes of peripheral circuits. As a result, subtle defects at these minimum feature sizes can adversely impact product yield. Physical failure analysis (PFA) has often been used to determine the precise cause of these subtle defects. However, PFA is time consuming, destructive, and may not reveal all defects such as gate dielectric failure. Additional complexity of current memory cells such as the 8T SRAM memory cell disclosed by Chang et al., “Stable SRAM Cell Design for the 32 nm Node and Beyond,” 2005 Symposium on VLSI Technology, 8A-2, 128 (2005), further complicate PFA. Moreover, the 8T SRAM cell of Chang et al. further complicates characterization of individual memory cells in a functional memory circuit. Thus, there is a need to more accurately diagnose memory circuit defects without the time, expense, and complication of PFA.